.png){kind=icon}
.png){kind=icon}
Return
MdCSR: A Memory-Efficient Sparse Matrix Compression Format
.png){kind=icon}
PRE
AI
DOI：10.1109/LES.2025.3598189.png)
.png){kind=icon}
Original request for help.png){kind=icon}
Share.png){kind=icon}
Save
Abstract
En 中文
Efficient representation of sparse matrices is critical for reducing memory usage and improving performance in hardware-accelerated computing systems. This letter presents memory-efficient delta-compressed storage row (MdCSR), a novel sparse matrix format designed to improve both storage efficiency and execution speed. MdCSR replaces absolute column indices with compact relative offsets and selectively applies delta encoding, resulting in a more compact index structure. Compared to traditional formats, it achieves an average of 15.45% memory savings over compressed sparse row (CSR), 52.77% over dCSR, and around 20% reduction in execution time. A dedicated architecture for CSR to MdCSR compression is also presented, optimized for real-time and low-overhead FPGA deployment.
Keywords:
Sparse approximation
Memory management
Real-time systems
Encoding
Sparse matrices
Indexes
Field programmable gate arrays
compressed sparse row (CSR)
FPGA
sparse matrix compression
sparse representation
Journal
IF:
2
Papers:
101
Citations:
696