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Memory Efficient Decoder Architectures for Quasi-Cyclic LDPC Codes
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DOI：10.1109/TCSI.2008.922024.png)
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Abstract
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In this paper, we first propose parallel turbo-sum-product (PTSP) and turbo-shuffled-sum-product (TSSP) decoding algorithms for partly parallel decoder architectures of quasi-cyclic (QC) low-density parity-check (LDPC) codes. Our proposed algorithms not only achieve faster convergence and better error Performance than the sum-product (SP) decoding algorithm, but also need less memory in implementation. Then we propose a partly parallel decoder architecture based on our PTSP algorithm and implement it using FPGA. Our PTSP decoder architecture achieves significantly higher throughput and requires less memory than previously proposed decoder architectures with the same FPGA and LDPC code. Finally, to further reduce the memory requirement, we also propose a partly parallel decoder architecture based on our TSSP algorithm.
Keywords:
Low-density parity-check (LDPC) codes
quasi-cyclic (QC) codes
shuffled decoding
sum-product (SP) decoding
turbo decoding
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