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Memory-Efficient Polar Decoders
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DOI：10.1109/JETCAS.2017.2764421.png)
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Abstract
En 中文
Polar codes have gained a great amount of attention in the past few years, since they can provably achieve the capacity of a symmetric channel with a low-complexity encoding and decoding algorithm. As a result, polar codes have been selected as a coding scheme in the 5th generation wireless communication standard. Among different decoding schemes, successive-cancellation (SC) and SC list decoding yield good trade-off between error-correction performance and hardware implementation cost. However, both families of algorithms have large memory requirements. In this paper, we propose a set of novel techniques that aim at reducing the high-memory cost of SC-based decoders. These techniques are orthogonal to the specific decoder architecture considered, and can be applied on top of existing memory reduction techniques. We have designed and implemented different polar decoders on FPGA and also synthesized them in 65 nm TSMC CMOS technology to verify the effectiveness of the proposed memory reduction techniques. The benchmark decoders yield comparable or lower area occupation than the state of the art: the results show that the proposed methods can save up to 46% memory area occupation and 42% total area occupation compared with benchmark SC-based decoders.
Keywords:
Polar codes
successive-cancellation decoding
list decoding
hardware implementation
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