.png){kind=icon}
Return
Memristive Circuits for LDPC Decoding
.png){kind=icon}
PRE
AI
DOI：10.1109/JETCAS.2014.2361071.png)
.png){kind=icon}
Original request for help.png){kind=icon}
Share.png){kind=icon}
Save
Abstract
En 中文
We present design principles for implementing decoders for low-density parity check codes in CMOL-type memristive circuits. The programmable nonvolatile connectivity enabled by the nanowire arrays in such circuits is used to map the parity check matrix of an LDPC code in the decoder, while decoding operations are realized by a cellular CMOS circuit structure. We perform detailed performance analysis and circuit simulations of example decoders, and estimate how CMOL and memristor characteristics such as the memristor OFF/ON resistance ratio, nanowire resistance, and the total capacitance of the nanowire array affect decoder specification and performance. We also analyze how variation in circuit characteristics and persistent device defects affect the decoders.
Keywords:
Terms-Iterative decoding
memristors
parity check codes
AI Summary
Key information extracted from the uploaded paper, including a brief overview, abstract, background, key highlights, visual analysis, and future outlook.
Journal
IF:
3.8
Papers:
1.4K
Citations:
2.8K
Organization
Cited Papers
A Functional Hybrid Memristor Crossbar-Array/CMOS System for Data Storage and Neuromorphic Applications.png)
NANO LETTERS
NANO LETTERSIF9.1
PREAI
ShareSaveShareSave
ShareSaveShareSaveFlood Forecasting using Holt-Winters Exponential Smoothing Method and Geographic Information System2017 International Conference on Control, Electronics, Renewable Energy and Communications (ICCREC)
2017 International Conference on Control, Electronics, Renewable Energy and Communications (ICCREC)IF0
PREAI
ShareSaveCascade reaction of propargylic alcohols with hydroxylamine hydrochloride: facile synthesis of α,β-unsaturated oximes and nitrilesTetrahedron
TetrahedronIF0
PREAI
ShareSaveShareSave
View more