Minimal Aliasing Single-Error-Correction Codes for DRAM Reliability Improvement

doi:10.1109/ACCESS.2021.3059843

Minimal Aliasing Single-Error-Correction Codes for DRAM Reliability Improvement

2021-01-01

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Shankar Ganesh Ramasubramanian

DOI：10.1109/ACCESS.2021.3059843

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Abstract

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We discuss the problem of finding a minimal aliasing code among a class of systematic single-error-correction codes that are suitable to be implemented within DRAM die, as opposed to external ECC used in memory controller outside of DRAM chip. We prove a sharp lower bound of aliasing probability and propose a simple method to come up with a code that meets the bound. By an experiment, we also demonstrate that a randomly chosen code is likely to have much more aliasings with overwhelmingly high probability.

Keywords:

Error correction codes

Systematics

Parity check codes

DRAM chips

Decoding

Reliability

Licenses

In-DRAM error correcting code

minimal aliasing code

single error correction

Minimal Aliasing Single-Error-Correction Codes for DRAM Reliability Improvement

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