Model synthesis using boolean expression diagrams

doi:10.1016/j.ress.2019.02.019

Model synthesis using boolean expression diagrams

2019-06-01

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DOI：10.1016/j.ress.2019.02.019

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In this article, we propose a new method for fault tree analysis, called model synthesis, which comes in addition to traditional assessment techniques. It consists in rewriting the fault tree under study, or the set of minimal cutsets extracted from this fault tree, so to make some relevant information emerge. Our implementation of model synthesis relies on encoding Boolean formulas by means of zero-suppressed Boolean expression diagrams. Rewriting heuristics are efficiently implemented by means of local operations on these diagrams. A key feature of zero-suppressed Boolean expression diagrams is that they make it possible to perform partial normalization of Boolean formulas, avoiding in this way the exponential blow-up of calculation resources most of the other methods suffer from. We show how to take advantage of the architecture of the systems under study to guide rewriting heuristics. We illustrate the principles of model synthesis and of its implementation by means of examples.

Keywords:

Fault tree synthesis

Boolean expression diagrams

Boolean formulas

System architecture

Model synthesis using boolean expression diagrams

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