Multi-Bit Compute-In Memory Architecture Using a C-2C Ladder Network

doi:10.1109/TCSII.2023.3329261

Multi-Bit Compute-In Memory Architecture Using a C-2C Ladder Network

2024-06-01

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DOI：10.1109/TCSII.2023.3329261

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This brief uses the capacitive charge coupling method to present a multi-bit SRAM-based compute-in-memory (CIM) architecture in the analog domain. The proposed architecture consists of a 64 x 64 9T1C SRAM array performing 1024 MAC operations between input activation (4-bit) and weight (4-bit) in a cycle, and an optimized 4-bit Flash ADC is used for converting the analog MAC into digital output. This brief achieves a throughput of 455 GOPS and an energy efficiency of 1012 TOPS/W at 222 MHz, maintaining a very high signal margin of 54 mV. The achieved inference accuracy is 98% for MNIST and 86% for the CIFAR-10 data set. This proposed work is implemented on a 28 nm CMOS Technology node at 0.9 V supply.

Keywords:

Random access memory

Logic gates

Capacitors

Computer architecture

Common Information Model (computing)

Couplings

Transistors

Analog

accuracy

bitline

capacitor

compute in-memory (CIM)

energy

multi-bit

Multi-Bit Compute-In Memory Architecture Using a C-2C Ladder Network

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