Multi-layer bus minimization for SoC

Ya-Shu Chen

doi:10.1016/j.jss.2009.07.041

Multi-layer bus minimization for SoC

2010-01-01

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DOI：10.1016/j.jss.2009.07.041

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The deployment of multiple processing elements such as a microprocessor or a Digital Signal Processor in embedded systems often results in significant communication overheads. The challenge lies in resolving the communication cost minimization problem, while simultaneously satisfying the timing constraints of job executions. In this paper, we explore bus-layer minimization problems by first identifying factors that contribute to the NP-hardness of these problems. Existing proposed algorithms and NP-hard problems are then identified and elucidated. A simulated annealing algorithm is proposed and compared with heuristics-based algorithms to provide further insights for system designers. Lastly, a series of extensive simulations is carried out and a case study is presented to show comparisons among different approaches and workloads. (C) 2009 Elsevier Inc. All rights reserved.

Keywords:

Multi-layer bus

System-on-chip

HW/SW codesign

Scheduling

Multi-layer bus minimization for SoC

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