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Multi-mode operator for SHA-2 hash functions
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DOI：10.1016/j.sysarc.2006.09.006.png)
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Abstract
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We propose an improved implementation of the SHA-2 hash family, with minimal operator latency and reduced hardware requirements. We also propose a high frequency version at the cost of only two cycles of latency per message. Finally we present a multi-mode architecture able to perform either a SHA-384 or SHA-512 hash or to behave as two independent SHA-224 or SHA-256 operators. Such capability adds increased flexibility for applications ranging from a server running multiple streams to independent pseudorandom number generation. We also demonstrate that our architecture achieves a performance comparable to separate implementations while requiring much less hardware. (c) 2006 Elsevier B.V. All rights reserved.
Keywords:
FPGA
hash function
SHA-2 family
multi-mode operator
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