Multi-objective module partitioning design for dynamic and partial reconfigurable system-on-chip using genetic algorithm

N. Janakiraman

doi:10.1016/j.sysarc.2013.10.001

Return

Multi-objective module partitioning design for dynamic and partial reconfigurable system-on-chip using genetic algorithm

2014-01-01

PRE

N. Janakiraman *

P. Nirmal Kumar

DOI：10.1016/j.sysarc.2013.10.001

Original

Original request for help

Save

Abstract

En 中文

This paper proposes a novel architecture for module partitioning problems in the process of dynamic and partial reconfigurable computing in VLSI design automation. This partitioning issue is deemed as Hypergraph replica. This can be treated by a probabilistic algorithm like the Markov chain through the transition probability matrices due to non-deterministic polynomial complete problems. This proposed technique has two levels of implementation methodology. In the first level, the combination of parallel processing of design elements and efficient pipelining techniques are used. The second level is based on the genetic algorithm optimization system architecture. This proposed methodology uses the hardware/software co-design and co-verification techniques. This architecture was verified by implementation within the MOLEN reconfigurable processor and tested on a Xilinx Virtex-5 based development board. This proposed multi-objective module partitioning design was experimentally evaluated using an ISPD'98 circuit partitioning benchmark suite. The efficiency and throughput were compared with that of the hMETIS recursive bisection partitioning approach. The results indicate that the proposed method can improve throughput and efficiency up to 39 times with only a small amount of increased design space. The proposed architecture style is sketched out and concisely discussed in this manuscript, and the existing results are compared and analyzed. (C) 2013 Elsevier B.V. All rights reserved.

Keywords:

Multi-objective problem

Module partitioning solution

Genetic algorithm

SoC

FPGA

Dynamic and partial reconfiguration

AI Summary

Key information extracted from the uploaded paper, including a brief overview, abstract, background, key highlights, visual analysis, and future outlook.