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Multi-Rate Programmable Equalizer for M-PHY Serial Interface
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DOI：10.1109/TETC.2019.2893735.png)
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Abstract
En 中文
A programmable continuous-time linear equalizer (CTLE) for multi-rate high speed serial interfaces (HSSI) is proposed in this paper. Our solution is compliant with the multi-data rates of 1.45, 2.9, 5.8 and 11.6 Gbps specified by the M-PHY rev.4 HSSI standard for mobile applications. The specifications of the input short-term total jitter STTJ are analyzed demystifying the M-PHY standard. A STTJ generator which is implemented using the behavioral description language cadence verilog-A, is also proposed in order to optimize the CTLE operation and to improve the simulation time for jitter tolerance testing. The transfer function and the power consumption are programmable according to the data-rate and to the frequency band of the STDJ. The CTLE topology was designed and simulated in TSMC CMOS 65 nm process with 1.2 V supply voltage and dissipates 12.5 mA for 11.66 Gbps and the FoM is 0.12 pJ/bit/dB. The output deterministic jitter is around 2.5 ps for 11.66 Gbps.
Keywords:
Jitter
Standards
Generators
Gears
Equalizers
Hardware design languages
Synchronization
High-speed serial interfaces
jitter tolerance simulation
cadence verilog-A
M-PHY standard
linear equalizers
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