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Multidimensional Pareto Frontiers Intersection Determination and Processor Optimization Case Study
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DOI：10.1109/DSD.2019.00091.png)
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Abstract
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Almost all today's electronic devices are equipped with a processor. Different applications require and depend on different properties of the processor. For example, the fast growing field of Internet of Things depends on a long operation time of the devices when powered with batteries. Using general purpose processors has proved ineffective which led to a growing usage of Application-Specific Instruction-Set processors (ASIPs) which can be optimized for specific applications using different modifications of their properties (such as the number of registers, cache sizes, instruction set modifications, etc.). A suitable processor configuration can be hand-picked by a designer or by an automatic tool. The goal of this paper is to introduce a tool able to find a suitable processor configuration for multiple applications by constructing a compromise Pareto-optimal frontier of processor configurations. Experiments are based on a parametrizable RISC-V processor.
Keywords:
Pareto frontier
processor optimization
ASIP
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