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Neuron Array With Plastic Synapses and Programmable Dendrites
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DOI：10.1109/TBCAS.2013.2282616.png)
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Abstract
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We describe a novel neuromorphic chip architecture that models neurons for efficient computation. Traditional architectures of neuron array chips consist of large scale systems that are interfaced with AER for implementing intra- or inter-chip connectivity. We present a chip that uses AERfor inter-chip communication but uses fast, reconfigurable FPGA-style routing with local memory for intra- chip connectivity. We model neurons with biologically realistic channel models, synapses and dendrites. This chip is suitable for small-scale network simulations and can also be used for sequence detection, utilizing directional selectivity properties of dendrites, ultimately for use in word recognition.
Keywords:
Dendritic computation and processing
field programmable analog arrays (FPAA)
floating-gate devices
on-chip learning
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