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On-Chip Support for NoC-Based SoC Debugging
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DOI：10.1109/TCSI.2009.2034887.png)
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Abstract
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This paper presents a design-for-debug (DfD) technique for network-on-chip (NoC)-based system-on-chips (SoCs). We present a test wrapper and, a test and debug interface unit. They enable data transfer between a tester/debugger and a core-under-test (CUT) or -debug (CUD) through the available NoC to facilitate test and debug. We also present a novel core debug supporting logic to enable transaction-and scan-based debug operations. The basic operations supported by our scheme include event processing, stop/run/single-step and selective storage of debug information such as current state, time, and debug event indication. This allows internal visibility and control into core operations. Experimental results show that single and multiple stepping through transactions are feasible with moderately low area overhead.
Keywords:
Design-for-debug (DfD)
design-for-testability (DfT)
digital system testing
network-on-chip (NoC)
system-on-chip (SoC)
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