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On Using Lossy Compression for Repeatable Experiments during Silicon Debug
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DOI：10.1109/TC.2010.122.png)
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Abstract
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The amount of data that is observed during at-speed silicon debug is limited by the capacity of the on-chip trace buffers. To increase the debug observation window, we propose a low-cost debug architecture for at-speed silicon debug based on lossy compression. The proposed architecture enables a new debug methodology that accelerates the identification of the erroneous samples that occur intermittently over a long observation window by avoiding debug experiments that capture only error-free data. The proposed solution is applicable to both automatic test equipment-based debug and in-field debug on application boards, as long as the debug experiments are repeatable and the reference data at the probe signals are deterministically computed using a fast behavioral model of the circuit under debug.
Keywords:
Silicon debug
observation window
lossy compression
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PROCEEDINGS OF THE IEEE
PROCEEDINGS OF THE IEEEIF25.9
PREAI
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