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One-transistor static random-access memory cell array comprising single-gated feedback field-effect transistors
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DOI：10.1038/s41598-021-97479-x.png)
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Abstract
En 中文
In this study, we fabricated a 2 x 2 one-transistor static random-access memory (1T-SRAM) cell array comprising single-gated feedback field-effect transistors and examined their operation and memory characteristics. The individual 1T-SRAM cell had a retention time of over 900 s, nondestructive reading characteristics of 10,000 s, and an endurance of 10(8) cycles. The standby power of the individual 1T-SRAM cell was estimated to be 0.7 pW for holding the 0 state and 6 nW for holding the 1 state. For a selected cell in the 2 x 2 1T-SRAM cell array, nondestructive reading of the memory was conducted without any disturbance in the half-selected cells. This immunity to disturbances validated the reliability of the 1T-SRAM cell array.
Keywords:
LOW-POWER
SRAM CELL
LOW-VOLTAGE
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