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Optimal Single Constant Multiplication Using Ternary Adders
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DOI：10.1109/TCSII.2016.2631630.png)
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Abstract
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The single constant coefficient multiplication is a frequently used operation in many numeric algorithms. Extensive previous work is available on how to reduce constant multiplications to additions, subtractions, and bit shifts. However, on previous work, only common two-input adders were used. As modern field-programmable gate arrays (FPGAs) support efficient ternary adders, i.e., adders with three inputs, this brief investigates constant multiplications that are built from ternary adders in an optimal way. The results show that the multiplication with any constant up to 22 bits can be realized by only three ternary adders. Average adder reductions of more than 33% compared to optimal constant multiplication circuits using two-input adders are achieved for coefficient word sizes of more than five bits. Synthesis experiments show FPGA average slice reductions in the order of 25% and a similar or higher speed than their two-input adder counterparts.
Keywords:
Arithmetic
circuits
circuit optimization
digital arithmetic
field-programmable gate arrays (FPGAs)
fixed-point arithmetic optimization
mathematics
multiplying circuits
optimization methods
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