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Optimized Algorithms for FPGA-Based Acceleration of 5G-NR PDSCH Transmit Chain
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DOI：10.1109/tcsi.2026.3693075.png)
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Abstract
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This paper presents optimized algorithms and hardware architecture for field-programmable gate array (FPGA)-based acceleration of the fifth-generation (5G) new radio (NR) physical downlink shared channel (PDSCH). The paper proposes a modular multi-intellectual property (IP) architecture that supports variable data widths across different processing blocks to efficiently accommodate the wide dynamic range of transport block sizes and various modulation schemes. The proposed implementation on a system-on-chip (SoC) based custom board achieves a significant reduction in latency, generating the first set of modulated symbols within <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$32 \mu s$ </tex-math></inline-formula> for a subcarrier spacing (SCS) of 30KHz, within the duration of a single symbol of 5G frame. The complete chain delivers a throughput of 167 Mbps, power efficiency of 698.74 Mbps/W, energy consumption of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.39~m\mathrm {J}$ </tex-math></inline-formula>, and resource utilization of only 4.05% of the total programmable logic (PL) resources of target device, while maintaining a latency to meet 5G-NR frame boundaries, even for the maximum bandwidth allocation for PDSCH in frequency range 1 (FR1) using 64-quadrature amplitude modulation (QAM) modulation. These results demonstrate the effectiveness of the proposed FPGA-based architecture for scalable, low-latency, and energy-efficient PDSCH processing in real-time 5G physical layer deployments.
Keywords:
PDSCH
3GPP
physical layer
5G-NR
hardware implementation
FPGA
transport block
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