.png){kind=icon}
.png){kind=icon}
Return
Optimizing CAM-based instruction cache designs for low-power embedded systems
.png){kind=icon}
PRE
AI
DOI：10.1016/j.sysarc.2008.06.001.png)
.png){kind=icon}
Original request for help.png){kind=icon}
Share.png){kind=icon}
Save
Abstract
En 中文
Energy consumption and power dissipation are important concerns in the design of embedded systems and they will become even more crucial with finer process geometry, higher frequencies deeper pipe, lines and wider issue designs. In particular, the instruction cache consumes more energy than any other processor module, especially with commonly used highly associative CAM-based implementations. Two energy-efficient approaches for highly associative CAM-based instruction Cache designs are presented by means of using a segmented wordline and a predictor-based instruction fetch mechanism. The latter is based on the fact that not all instructions in a given I-cache fetch are Used due to taken branches. The proposed Fetch Mask Predictor unit determines which instructions in a cache access will actually be Used to avoid fetching any of the other instructions. Both proposed approaches are evaluated for an embedded 4-wide issue processor in 100 nm technology. Experimental results show average I-cache energy savings of 48% and overall processor energy savings of 19%. (c) 2008 Elsevier B.V. All rights reserved.
Keywords:
Embedded systems
Energy-efficient architectures
Fetch unit design
AI Summary
Key information extracted from the uploaded paper, including a brief overview, abstract, background, key highlights, visual analysis, and future outlook.
Journal
IF:
4.1
Papers:
3.0K
Citations:
4.2K
