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Parallel Architecture for Battery Charge Equalization
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DOI：10.1109/TPEL.2014.2364838.png)
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Abstract
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One limitation of many battery charge equalizers is their slow equalization speed, especially when there are a large number of batteries in the series-string in high-voltage and high-power applications. This paper presents a new architecture for battery charge equalization. In this architecture, independent equalizers are placed in different layers and all the layers can equalize the corresponding batteries simultaneously, thus reducing equalization time by 50%. We explore the operation, performance characteristics, and the design of the architecture. Both simulation and experimental results are presented to validate the analysis in this paper.
Keywords:
Battery
charger
dc-dc converters
equalizers
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