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Parallel Pipelined Architecture and Algorithm for Matrix Transposition Using Registers
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DOI：10.1109/TCSII.2021.3134710.png)
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Abstract
En 中文
In this brief, we present a new algorithm and architecture for continuous-flow matrix transposition using registers. The algorithm supports P-parallel matrix transposition. The hardware architecture reaches the theoretical minimums in terms of latency and memory. It is composed of a group of identical cascaded basic swap circuits, whose stages are determined by the corresponding algorithm, and can be controlled via a set of counters. Compared with the state-of-the-art architecture, the proposed architecture supports matrices whose rows and columns are integer multiples of P. Here P can be arbitrary, including but not limited to power-of-two integers. Moreover, our results provide additional insight into continuous-flow non-square matrix transposition.
Keywords:
Computer architecture
Arrays
Hardware
Signal processing algorithms
Registers
Parallel processing
Circuits and systems
Pipelined algorithm
hardware architecture
continuous-flow
matrix transposition
parallel computing
Journal
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4.9
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8.8K
Citations:
2.5W