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Parallelize Memory Oriented Manual tiling-based energy-efficient non-neural face recognition algorithm on GAP8
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DOI：10.1016/j.sysarc.2026.103876.png)
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Abstract
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The feature extraction poses a novel challenge at resource-constrained edge nodes, owing to limited computational power and memory. To reduce execution time and energy consumption, this work parallelize non-neural algorithm inference while maintaining comparable accuracy. A hardware-friendly mixed-precision training data (8-bit fixed-point and 32-bit floating-point) is considered in this work to achieve higher accuracy while reducing the memory footprint by 14.95× and the overall cycle count by 55.75%. Additionally, deploying a Memory Oriented Manual tIling (MOMAI)-based non-neural face recognition (FR) algorithm on the GAP8 cluster reduces energy consumption. Compared to the non-DMA non-quantized (NDNQ) manually tiled version, the half manually-tiled non-quantized (HMTNQ) model and the fully manually-tiled 8-bit quantized (FMTQ) approach reduce energy consumption by 88.35% and 94%, respectively. Compared to the NDNQ manually tiled version, DMA-based half (HMTNQ) and full (FMTQ) manual-tiling reduces recognition time by 7.64× and 16.09× on 8 cores, and by 7.95× and 134.32× on a single core, respectively. Compared to the NDNQ approach on the ARM Cortex-M7, the parallelized (8-core) HMTNQ and FMTQ implementations of Eigenfaces-based face recognition on GAP8 require 34% and 70.15% fewer cycles, respectively, while maintaining an accuracy of 93%.
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