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Parallelizing Iris Recognition
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DOI：10.1109/TIFS.2009.2032012.png)
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Abstract
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Iris recognition is one of the most accurate biometric methods in use today. However, the iris recognition algorithms are currently implemented on general purpose sequential processing systems, such as generic central processing units (CPUs). In this work, we present a more direct and parallel processing alternative using field-programmable gate arrays (FPGAs), offering an opportunity to increase speed and potentially alter the form factor of the resulting system. Within the means of this project, the most time-consuming operations of a modern iris recognition algorithm are deconstructed and directly parallelized. In particular, portions of iris segmentation, template creation, and template matching are parallelized on an FPGA-based system, with a demonstrated speedup of 9.6, 324, and 19 times, respectively, when compared to a state-of-the-art CPU-based version. Furthermore, the parallel algorithm on our FPGA also greatly outperforms our calculated theoretical best Intel CPU design. Finally, on a state-of-the-art FPGA, we conclude that a full implementation of a very fast iris recognition algorithm is more than feasible, providing a potential small form-factor solution.
Keywords:
Biometrics
field-programmable gate arrays (FPGAs)
iris recognition
parallel computing
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