.png){kind=icon}
.png){kind=icon}
Return
Pattern-Integrated Interference Lithography: Prospects for Nano- and Microelectronics
.png){kind=icon}
OA
AI
DOI：10.1364/OE.20.023643.png)
.png){kind=icon}
.png){kind=icon}
Share.png){kind=icon}
Save
Abstract
En 中文
In recent years, limitations in optical lithography have challenged the cost-effective manufacture of nano-and microelectronic chips. Spatially regular designs have been introduced to improve manufacturability. However, regular designed layouts typically require an interference step followed by a trim step. These multiple steps increase cost and reduce yield. In the present work, Pattern-Integrated Interference Lithography (PIIL) is introduced to address this problem. PIIL is the integration of interference lithography and superposed pattern mask imaging, combining the interference and the trim into a single-exposure step. Example PIIL implementations and experimental demonstrations are presented. The degrees of freedom associated with the source, pattern mask, and Fourier filter designs are described. (C) 2012 Optical Society of America
Keywords:
OPTICAL LITHOGRAPHY
DESIGN
PHOTOLITHOGRAPHY
RESOLUTION
MASK
AI Summary
Key information extracted from the uploaded paper, including a brief overview, abstract, background, key highlights, visual analysis, and future outlook.