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Physics-Grounded Probabilistic Bits for Hardware-Efficient Intelligent Inference and Optimization
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DOI：10.1002/aisy.70469.png)
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Abstract
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As intelligent systems increasingly rely on probabilistic inference and large-scale optimization, deterministic hardware faces intrinsic limitations in efficiently exploring complex solution spaces. Here, we present a physics-grounded probabilistic bit (p-bit) that serves as a hardware-native primitive for energy-efficient intelligent inference and optimization. The proposed p-bit exploits intrinsic stochastic electron capture in a multitrap ensemble at the Si–SiNx interface, converting nanoscale defect dynamics into a controllable probabilistic output fully compatible with standard complementary metal–oxide–semiconductor technology. A width-programmed gate-pulse scheme enables robust and continuous probability modulation by controlling trap occupancy through pulse duration rather than voltage amplitude, improving scalability and tolerance to interconnect nonidealities. We develop a physics-based analytical framework that quantitatively links multitrap capture kinetics to macroscopic drain-current statistics and implement it as a SPICE (Simulation Program with Integrated Circuit Emphasis)-compatible compact model, enabling direct cosimulation with conventional digital circuits. The resulting p-bit exhibits a Boltzmann-consistent sigmoid activation, supporting experimentally validated invertible logic and bidirectional probabilistic inference. Using experimentally calibrated characteristics, networks of these p-bits solve a 50-variable, 218-clause 3-satisfiability benchmark via controlled stochastic energy minimization, demonstrating system-level relevance for intelligent optimization. This work establishes a scalable pathway toward hardware-efficient probabilistic computing architectures for intelligent systems.
Keywords:
computer science
inference
integrated circuit
probabilistic logic
scalability
Simulation Program with Integrated Circuit Emphasis
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