.png){kind=icon}
.png){kind=icon}
Return
pixcore, RISC-V microprocessor with integrated pixel matrix management unit
.png){kind=icon}
PRE
AI
DOI：10.1088/1748-0221/21/01/P01015.png)
.png){kind=icon}
Original request for help.png){kind=icon}
Share.png){kind=icon}
Save
Abstract
En 中文
This paper presents pixcore, which is a 32-bit RISC-V microprocessor with an integrated pixel matrix management coprocessor. The integration of the coproccessor with a RISC-V core enabled the management of the pixel matrix using custom RISC-V instructions, allowing for high performance and flexibility. The presented solution was designed in a 16 nm FinFET CMOS process, and the results of the chip implementation were used in post-layout simulations. The conducted simulations confirmed that the developed coproccessor can be successfully used for managing and readout of the hybrid pixel detector. A comparison was made between the proposed solution and the microprocessor-based system that utilized a dedicated peripheral device for the purpose of controlling the pixel matrix. The comparison indicates a reduction in the execution time of the selected algorithms by a factor of 14, measured in terms of clock cycles.
Keywords:
Detector control systems (detector and experiment monitoring and slow-control systems, architecture, hardware, algorithms, databases)
Digital electronic circuits
Hybrid detectors
VLSI circuits
Journal
IF:
1.3
Papers:
582
Citations:
1.3W