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Power Efficient Motion Estimation Algorithm and Architecture Based on Pixel Truncation
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DOI：10.1109/TCE.2011.6131154.png)
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Abstract
En 中文
A new block matching algorithm and its VLSI architecture for performing Motion Estimation (ME) are presented in this paper. In the reported fast two stage search algorithm, ME is performed in two stages. In the first stage, pixel truncation is used. In the second stage, ME is performed with full pixel resolution with an adaptive search pattern. The main advantage of the proposed algorithm is the inclusion of an early termination mechanism to reduce overall power consumption for the resulting architecture. The paper also introduces a suitable architecture to implement the proposed ME algorithm. In this architecture, a new memory management scheme has been proposed so that different bit planes can be accessed at different stages of ME from the same memory module. It has been shown that the proposed architecture can save approximately 27% power compared to another recently reported architecture. The proposed architecture can therefore be considered suitable for portable, battery-powered video consumer devices(1).
Keywords:
Low power design
variable block size motion estimation architecture
pixel truncation
fast two stage search algorithm
adaptive search pattern
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