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Power Supply Ripple Rejection Analysis of Low-Dropout Regulators With a Buffer Stage
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DOI：10.1109/tcsi.2026.3687445.png)
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Abstract
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This article presents a method for the analysis of power supply rejection (PSR) of low-dropout regulators (LDOs), especially for those with a buffer stage. To determine the optimal design combination for each block in an LDO, we analyze and categorize ripple-coupling paths in LDOs with a buffer stage using a small-signal model based on the open-loop PSR concept. High frequency characteristics of the LDO power stage with and without an off-chip load capacitor are also analyzed in detail to extend the proposed method to very high frequencies, and to optimize the PSR performance at high frequencies. And then the co-design of open-loop PSR and feedback loop dynamics is analyzed to facilitate an informed design procedure for optimized overall PSR. Finally, we implement an output-capacitorless LDO with a buffer stage to verify the analyses in this work. In this design example, the effects of the reduced r<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ds</sub> of the power transistor in an advanced process with very low dropout voltage are discussed and a feed forward ripple cancellation (FFRC) scheme is implemented to further enhance the PSR performance.
Keywords:
Low dropout regulators (LDO)
power supply rejection (PSR)
gate drive buffer
frequency response
transfer function
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