Practical Strategies for Power-Efficient Computing Technologies

doi:10.1109/JPROC.2009.2035451

Practical Strategies for Power-Efficient Computing Technologies

2010-02-01

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DOI：10.1109/JPROC.2009.2035451

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After decades of continuous scaling, further advancement of silicon microelectronics across the entire spectrum of computing applications is today limited by power dissipation. While the trade-off between power and performance is well-recognized, most recent studies focus on the extreme ends of this balance. By concentrating instead on an intermediate range, an similar to 8 x improvement in power efficiency can be attained without system performance loss in parallelizable applications-those in which such efficiency is most critical. It is argued that power-efficient hardware is fundamentally limited by voltage scaling, which can be achieved only by blurring the boundaries between devices, circuits, and systems and cannot be realized by addressing any one area alone. By simultaneously considering all three perspectives, the major issues involved in improving power efficiency in light of performance and area constraints are identified. Solutions for the critical elements of a practical computing system are discussed, including the underlying logic device, associated cache memory, off-chip interconnect, and power delivery system. The IBM Blue Gene system is then presented as a case study to exemplify several proposed directions. Going forward, further power reduction may demand radical changes in device technologies and computer architecture; hence, a few such promising methods are briefly considered.

Keywords:

Circuit optimization

CMOS digital integrated circuits

CMOSFETs

integrated circuit design

integrated circuit interconnections

parallel machines

power distribution

Practical Strategies for Power-Efficient Computing Technologies

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