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Predicting performance in multi-core systems with shared reconfigurable accelerators
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DOI：10.1016/j.sysarc.2019.07.010.png)
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Abstract
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Reconfigurable multi-core architectures, where general-purpose processors are extended with reconfigurable logic, present an interesting design choice for their capacity of efficiently executing both sequential as well as parallel workloads. Current state-of-the-art implementations distinguish between dedicated accelerators (where each core has access to its own reconfigurable fabric, for maximum performance) and shared ones (where a reconfigurable fabric is shared among cores, for maximum resource utilization), but no design-time guidance is provided for choosing the best implementation. In this work, we propose a new metric to guide the design of shared reconfigurable accelerators (independent of the hardware implementation) in multi-core environments by numerically assessing their rate of concurrency. We evaluate it with an 8-core system where any given number of coarse-grained reconfigurable arrays supporting transparent acceleration (i.e. with no changes in the binary) are available to execute multi-threaded applications. Using performance simulation from gems, we show that while poorly correlated with an application's thread-level parallelism (TLP), the proposed metric correlates strongly with the speedup achieved when switching from a shared fabric to dedicated per-core accelerators, and therefore can aid the designer in choosing the best strategy for implementing a reconfigurable multi-core architecture.
Keywords:
Reconfigurable architectures
Multi-core architectures
Thread-level parallelism
Performance prediction
Performance metrics
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