Probabilistic Analysis for Sequential Circuits Verification Using Markov Chains

doi:10.1109/TCSII.2020.3005705

Probabilistic Analysis for Sequential Circuits Verification Using Markov Chains

2021-01-01

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DOI：10.1109/TCSII.2020.3005705

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Random testing is used extensively in functional verification of hardware systems. In practice, testing stops when a certain coverage criterion is achieved. However, testing has the inherent problem of being only able to expose bugs, not prove their absence. Thus, proving whether a potential bug exists or not under current verification efforts would be helpful to measure the completeness of testing. This brief proposes a probabilistic coverage analysis method to quantify the probability of bug existence for sequential circuit verification under random testing. The proposed method consists of an effective formula for computing the probability of a bug (assuming it exists) being detected in a sequential circuit. The formula is time complexity cubic to the number of coverage bins and linear to the number of test cycles. To validate the proposed method, it was implemented in MATLAB to calculate the probability of a bug being detected. Experimental results on 20,116 random instances indicate that, using Monte Carlo simulation, the proposed analysis method has an average absolute relative error of approximately 0.027%, comparing to 7.38% in existing work.

Keywords:

Computer bugs

Circuit faults

Sequential circuits

Testing

Probabilistic logic

Markov processes

Integrated circuit modeling

Coverage analysis

Markov chains

sequential circuits verification

temporal behavior

Probabilistic Analysis for Sequential Circuits Verification Using Markov Chains

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