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Probabilistic optimization for FPGA board level routing problems
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DOI：10.1109/TCSII.2005.859569.png)
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Abstract
En 中文
Field programmable gate arrays (FPGAs) are an enabling technology in circuit designs. We consider the board-level multi-terminal net assignment in the FPGA-based logic emulation. A novel probabilistic optimization method is devised for solving the net assignment problem. The approach incorporates randomized rounding, genetic algorithm, and solution-improvement strategies. Experimental results demonstrate promising performance.
Keywords:
board-level routing
Chernoff bound
field programmable gate array (FPGA)
randomized rounding
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