Probabilistic Verification for Modular Network-on-Chip Systems

doi:10.1007/978-3-032-15700-3_18

Probabilistic Verification for Modular Network-on-Chip Systems

2026-01-01

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DOI：10.1007/978-3-032-15700-3_18

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Quantitative verification can provide deep insights into reliable Network-On-Chip (NoC) designs. It is critical to understanding and mitigating operational issues caused by power supply noise (PSN) early in the design process: fluctuations in network traffic in modern NoC designs cause dramatic variations in power delivery across the network, leading to unreliability and errors in data transfers. Further complicating these challenges, NoC designs vary widely in size, usage, and implementation. This case study paper presents a principled, systematic, and modular NoC modeling approach using the MODEST language that closely reflects the standard hierarchical design approach in digital systems. Using the MODEST TOOLSET, functional and quantitative correctness was established for several NoC models, all of which were instantiated from a generic modular router model. Specifically, this work verifies the functional correctness of a generic router, inter-router communication, and the entire NoC. Statistical model checking was used to verify PSN-related properties for NoCs of size up to 8 x 8.

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POWER

Probabilistic Verification for Modular Network-on-Chip Systems

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