Process variation aware DRAM-Cache resizing

Bindu Agarwalla

doi:10.1016/j.sysarc.2021.102364

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Process variation aware DRAM-Cache resizing

2022-02-01

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Bindu Agarwalla

Shirshendu Das *

Nilkanta Sahu

DOI：10.1016/j.sysarc.2021.102364

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Abstract

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As the demand for larger-sized Last Level Cache (LLC) grows due to modern data-intensive applications, employing low-density SRAM technology to create the LLC for the multicore system is no longer advantageous. Because capacity is more essential than latency in LLC, employing high-density DRAM technology to design LLC is an alternative approach. However, in order to employ DRAM as an LLC, several of its fundamental disadvantages must be effectively addressed. The DRAM-LLC is typically used in die-stacking technology, where the LLC is layered on top of the core layer. The LLC is also separated into several banks. Though larger-sized LLCs are preferred for data-intensive applications, they are not required for all applications. To lower the energy consumption of DRAM-LLC, the size of the LLC can be reduced by shutting down some unused component (bank) of the LLC. These powered-off banks can be reopened whenever the LLC capacity is increased. LLC resizing is the name of the procedure. Because of manufacturing variance, the entire DRAM-LLC does not react evenly. The section affected by process variation has higher delay and energy consumption than the other portions. In this paper, we propose a Process Variation Aware LLC Resizing (PVAR), in which the shrinkage is accomplished by shutting down the affected banks. The existing resizing strategies primarily target underused banks, but these underused banks may be healthy, and instead of powering down these banks, powering down the affected bank is more useful. Experiment results demonstrate that the suggested LLC resizing reduces energy usage by up to 47% more than existing solutions.

Keywords:

DRAM Cache

Energy saving

Tiled CMP

Cache resizing