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Programmable hardware architectures for sensor validation
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DOI：10.1016/0967-0661(96)00144-X.png)
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Abstract
En 中文
A previous paper (Henry, 1995a) introduced the technique of hardware compilation as the basis for developing highly flexible programmable hardware platforms for control applications such as sensor validation. This paper describes two PC-hosted architectures for sensor validation research. The first holds up to two FPGAs and supports a daughter board with application-specific circuitry. The second is based on the transputer TRAM standard, and consists of programmable hardware modules providing interfacing and low-level signal processing between the transputer and arbitrary I/O components. Three applications are described, based upon a thermocouple, a dissolved oxygen probe and a Coriolis mass flow meter.
Keywords:
Field-Programmable Gate Analysis (FPGAs)
hardware compilation
Handel
occam
transputers
sensor validation
uncertainty
fault detection and diagnosis
fieldbus
thermocouple
dissolved oxygen sensing
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