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Pruning random resistive memory for optimizing analog AI
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DOI：10.1038/s41467-025-67960-6.png)
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Abstract
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The rapid expansion of AI models has intensified concerns over energy consumption. Analog in-memory computing with resistive memory offers a promising, energy-efficient alternative, yet its practical deployment is hindered by programming challenges and device non-idealities. Here, we propose a software-hardware co-design that trains randomly weighted resistive-memory neural networks via edge-pruning topology optimization. Software-wise, we tailor the network topology to extract high-performing sub-networks without precise weight tuning, enhancing robustness to device variations and reducing programming overhead. Hardware-wise, we harness the intrinsic stochasticity of resistive-memory electroforming to generate large-scale, low-cost random weights. Implemented on a 40 nm resistive memory chip, our co-design yields accuracy improvements of 17.3% and 19.9% on Fashion-MNIST and Spoken Digit, respectively, and a 9.8% precision-recall AUC improvement on DRIVE, while reducing energy consumption by 78.3%, 67.9%, and 99.7%. We further demonstrate broad applicability across analog memory technologies and scalability to ResNet-50 on ImageNet-100. AI models consume growing amounts of energy. Here, the authors introduce a brain-inspired way to prune connections in randomly weighted resistive-memory chips, boosting accuracy while avoiding costly analog tuning to improve general efficiency and reduce power use.
Keywords:
Analog AI
Resistive memory
Neural network pruning
Energy efficiency
Software-hardware co-design
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