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Quick-Div: Rethinking Integer Divider Design for FPGA-based Soft-processors
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DOI：10.1145/3502492.png)
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Abstract
En 中文
In today's FPGA-based soft-processors, one of the slowest instructions is integer division. Compared to the lowsingle-digit latency of other arithmetic operations, the fixed 32-cycle latency of radix-2 division is substantially longer. Given that today's soft-processors typically only implement radix-2 division-if they support hardware division at all-there is significant potential to improve the performance of integer dividers. In this work, we present a set of high-performance, data-dependent, variable-latency integer dividers for FPGA-based soft-processors thatwe call Quick-Div. We compare them to various radix-N dividers and provide a thorough analysis in terms of latency and resource usage. In addition, we analyze the frequency scaling for such divider designs when (1) treated as a stand-alone unit and (2) integrated as part of a high-performance soft-processor. Moreover, we provide additional theoretical analysis of different dividers' behaviour and develop a new better-performing Quick-Div variant, called Quick-radix-4. Experimental results show that our Quick-radix-4 design can achieve up to 6.8x better performance and 6.1x better performance-per-LUT over the radix-2 divider for applications such as random number generation. Even in cases where division operations constitute as little as 1% of all executed instructions, Quick-radix-4 provides a performance uplift of 16% compared to the radix-2 divider.
Keywords:
operator
integer divider
variable-latency pipeline
soft-processor
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