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Real Time Receiver Baseband Processing Platform for Sub 6 GHz PHY Layer Experiments
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DOI：10.1109/ACCESS.2020.3000127.png)
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Abstract
En 中文
Wireless communication is rapidly evolving to fulfill diverse requirements in a number of application areas. Researchers are experimenting with novel ideas to improve different aspects of communication systems and performance metrics. While computer simulation is the first step to validating these approaches, testing platforms are needed to transform them to implementations for further validation and experimentation. Software Defined Radios (SDR) and System on Chip (SoC) offer a great deal of flexibility and versatility allowing researchers to experiment with wireless algorithms. However there are challenges; noise, channel effects, and synchronization errors have to be dealt with, and measures to mitigate their effects on received symbols should be implemented. Existing research using state of the art SDR platforms has not leveraged the powerful processing capabilities of Field Programmable Gate Arrays (FPGAs) in SoCs for receiver backend operations. In this work, we use high level tools to describe hardware, and automatically synthesize and implement receiver baseband wireless signal processing algorithms for FPGA targets. We demonstrate the ability to use such platforms for real world applications using over the air waveforms. We use Xilinx ZC706, Zedboard, ADI's FMComms3, and NXP's BGA7210 variable gain amplifier (VGA) for the experiments presented in this paper. Use cases considered include testing the performance of higher order modulation schemes, adjacent channel interference, power amplifier (PA) gain compression and effects on the bit error rate (BER) performance.
Keywords:
FPGA
software defined radio
wireless communication
channel estimation
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