Reconfigurable and hardware efficient adaptive quantization model-based accelerator for binarized neural network

doi:10.1016/j.compeleceng.2022.108302

Reconfigurable and hardware efficient adaptive quantization model-based accelerator for binarized neural network

2022-09-01

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Subramaniyaswamy, V *

DOI：10.1016/j.compeleceng.2022.108302

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Binarized neural networks (BNNs) architecture play a vital role in the development of deep learning accelerator for memory-constrained IoT devices. However, the cost-efficiency of the domain-specific accelerators still requires a simplified structure to enhance the computing performance of BNNs. We propose and present a reconfigurable BNN accelerator to improve the computing speed through channel amplitude and an adaptive spatial amplitude model. To reduce the redundant operations in the binarization of matrix multiplication, we introduce the channel amplitude model for BNN convolution functions. The adaptive spatial amplitude is implemented with the help of a matrix multiplication layer with 3 x 3 convolutions to get spatial information and increases the computation speed. For hardware implementation, the channel amplitude conversion is deployed through XNOR-popcount convolutions of each layer. The performance results of our proposed accelerator provide 2-10 x line buffer efficiency, 1.6-3.7 x processing frequency enhancement, and 2.35 x processing element reduction compared with existing baselines using VGG-16 based FPGA implementation.

Keywords:

Binarized neural network

Deep learning

Hardware accelerator

Adaptive spatial amplitude

FPGA

Reconfigurable and hardware efficient adaptive quantization model-based accelerator for binarized neural network

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