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Redesign and Accelerate the TIP4P Water Model on the New-Generation Sunway Supercomputer
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DOI：10.1016/j.jpdc.2026.105271.png)
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Abstract
En 中文
• We propose SW_TIP4P, a novel TIP4P water model algorithm tailored for the Sunway architecture, achieving deep adaptation to the architectural features of Sunway processors. • We implement a multi-threaded parallel TIP4P algorithm that efficiently leverages the computing power of the CPEs, accelerating the computationally intensive neighbor list and force calculation modules. • We introduce an AoS (Array-of-Structures)-based data layout strategy to compactly store atomic information, improving DMA transfer efficiency and memory access performance. • We propose a thread-private, software cache method to eliminate write conflicts. This cache resides in the LDM of each CPE and ensures data consistency between LDM and main memory. • We propose a shared-LDM based memory access strategy that enables atomic data sharing among 64 CPEs within the same core group (CG), effectively reducing redundant memory access overhead. • In experimental tests, we have scaled the number of atoms to the millions and achieved a parallel efficiency of 83.6%-88.2% on 12,480 cores (= 192 processes × (1 MPE + 64 CPEs)). This indicates that with continued increases in computing resources, the atomic scale can be expanded to tens of millions or even larger.
Keywords:
SW_TIP4P
TIP4P water model
Sunway supercomputer
parallel computing
memory access strategy
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