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Reduced Check Node Storage for Hardware-Efficient LDPC Decoder

delete2026-04-01
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PRE
AI
T
Tran-thi, Bich Ngoc *
L
Le, Trong Hai
DOI：10.13164/re.2026.0056delete
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Abstract

Abstract

En 中文
This paper proposes a hardware-and memory-efficient architecture for Low-Density Parity-Check (LDPC) decoding, targeting enhanced-performance applications with constrained resources. The design integrates two novel techniques: (i) the Variable Single minimum Min-Sum (VSMS) algorithm, which reduces hardware complexity by identifying the first minimum value and its position during check node processing, while improving error correction through a correction factor applied in variable node updates; and (ii) a memory splitting strategy that exploits the structural properties of LDPC codes to optimize memory usage. Implementation on a Xilinx Kintex UltraScale+ (xcku5p) FPGA demonstrates a reduction in storage requirements by over 46.2% compared to conventional decoders. Furthermore, the proposed decoder achieves a performance gain of up to 0.38 dB at a Bit Error Rate (BER) of 10(-8), outperforming traditional Min-Sum-based approaches.
Keywords:
5G NR
error correction
FPGA
LDPC decoder
VSMS algorithm

Journal

R
Radioengineering
IF:
0.7
Papers:
37
Citations:
994

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No organization information available