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Resource-Efficient Parallel Tree-Based Join Architecture on FPGA
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DOI：10.1109/TCSII.2018.2836920.png)
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Abstract
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The offloading and acceleration of database operations on field programmable gate arrays (FPGAs) have been extensively studied for a long time. Architectures of join, a key database operation, have been proposed and optimized on FPGAs. However, these join architectures are either resource-intensive or have low-throughput. In this brief, we focus on the equi-join and propose a resource-efficient join architecture based on a tree model. The architecture needs two phases: the build phase, in which a binary tree is built by using the first database table, and the probe phase, in which the architecture searches the tree to find matching solutions through a second database table. In addition, we propose a parallel implementation for this architecture to improve its performance. The proposed design was implemented on a Xilinx FPGA, and the results were compared with the most recent works on hardware join. The experimental results demonstrate that for a range of parallelism and dataset sizes, our design achieves a data throughput of 8-100 million tuples per second, which is compatible with the bus rate, and performs well in balancing resource utilization and data throughput.
Keywords:
FPGA
database
hardware acceleration
equi-join
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