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Revising NoC in Future Multicore-Based Consumer Electronics for Performance
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DOI：10.1109/MCE.2021.3062001.png)
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Abstract
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With the increasing demand for efficient data processing, the latest consumer electronics are powered by multicore processors. Many applications that run on these devices expect minimum data access latency, where network-on-chip (NoC) plays a crucial role. However, NoC is found to be responsible for 60%-75% of miss penalty. The objective of this article is to present a revised NoC communication framework that can possibly reduce the miss penalty. The proposed architecture orchestrates buffers of NoC routers as a victim cache to store evicted cache blocks. Future references to such stored blocks are replied from NoC routers, which significantly reduces miss penalty and improves system performance. Minimizing miss penalty by maximizing NoC resource utilization in these devices is a win-win situation.
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