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RISC-HD: Lightweight RISC-V Processor for Efficient Hyperdimensional Computing Inference
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DOI：10.1109/JIOT.2022.3191717.png)
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Abstract
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Hyperdimensional (HD) computing is a lightweight machine learning method widely used in Internet of Things applications for classification tasks. Although many hardware accelerators are proposed to improve the performance of HD, they suffer from low flexibility that makes them not practical in most real-life scenarios. To improve the flexibility, an opensource instruction set architecture (ISA) called RISC-V has been employed and extended for a specific application such as machine learning. This article aims to improve the efficiency and flexibility of HD computing for resource-constrained applications. To this end, we extend a RISC-V core (RI5CY) for HD computing called RISC-HD. First, to reduce the computational overhead at the HD inference phase, we introduce a pruning method to remove the ineffectual dimensions. The proposed pruning method can reduce the dimension from 10k to 1k with negligible accuracy loss. Second, an ISA extension for RI5CY is proposed to compute the HD inference efficiently. Experimental results indicate that RISC-HD adds 1.42x area overhead to the RI5CY core; however, it consumes only 2932 slices on the Artix-7 FPGA, which is suitable for resource-constrained devices. Additionally, RISC-HD improves the total clock cycle by 7.48x compared to the RI5CY core and 6.17x compared to ARM Cortex-M4 in the ISOLET data set. Moreover, RISC-HD achieves 7.22x energy efficiency compared to the RI5CY core.
Keywords:
FPGA design
hyperdimensional (HD) computing
instruction set architecture (ISA) extension
pruning
RISC-V
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