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RISCing it All: Accelerating Binary Translation Using Software-Only Validated Flag Speculation
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DOI：10.1109/tmc.2026.3718184.png)
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Abstract
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ARM processors are expanding beyond mobile devices into laptops, desktops, and servers, yet the x86 software ecosystem remains a barrier to adoption. Dynamic binary translation provides a practical compatibility path, but performance is often limited by condition code handling. x86 implicitly updates EFLAGS after most arithmetic operations, whereas ARM updates condition codes only on request and lacks hardware support for all x86 flags. Conservative translation therefore materializes flags in software, inflating instruction counts and placing flag extraction on critical paths. We present Cascade, a software-only x86-to-ARM64 binary translation framework that substantially reduces EFLAGS overhead through three complementary techniques. First, backward per-flag liveness analysis identifies provably unused flag updates, and a persistent cache amortizes the cost of this analysis across executions. Second, for remaining live flags, Cascade maps SF, ZF, CF, and OF directly to ARM NZCV when semantics permit, forwards carry state through the hardware carry chain across ADC and SBB sequences, and fuses common test-and-branch idioms into single ARM instructions. Third, Cascade propagates flag validity across translation block boundaries using per-block interface summaries, guiding code generation so that a block reads flags its predecessors have already established, rather than recomputing them, wherever the cross-block requirement can be proven. We implement Cascade in Box64 and evaluate it on three ARM platforms. Cascade improves 7-Zip LZMA throughput by up to 2.4×, increases Geekbench 6 multi-core scores by up to 36%, and improves Unigine Heaven and Valley benchmark scores by up to 10.6%, with modest compilation overhead.
Keywords:
ARM architecture
x86 architecture
binary translation
software portability
mobile computing
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