RRAM Circuit-Enabled Nonlinear Precoding and Bit Precision Analysis

doi:10.1109/tcomm.2026.3726722

RRAM Circuit-Enabled Nonlinear Precoding and Bit Precision Analysis

2026-08-24

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DOI：10.1109/tcomm.2026.3726722

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The rising number of users and antennas imposes exponentially growing computational loads on future communication systems. Yet conventional processors are facing a bottleneck for their nature of memory-computing separation. In-memory computing (IMC) emerges as a promising solution leveraging its intrinsic high parallelism. This work proposes an IMC architecture that employs resistive random access memory (RRAM) to reduce the computational complexity of the nonlinear Tomlinson-Harashima precoding (THP) to a linear scale. We present a computation-constraint principle for designing RRAM circuits to perform nonlinear matrix operations and construct an LQ decomposition RRAM circuit. Since the conductance of memristor is generally quantized, we perform the bit precision analysis and derive the lower bound of the Signal-to-Interference-plus-Noise Ratio (SINR) and achievable rate. Our analysis indicates that at a high Signal-to-Noise Ratio (SNR) or with a large number of antennas, each 1-bit precision increase yields 6 dB SINR gain and linear rate growth. For practical implementation, we derive the optimal bit precision to sustain SINR performance under varying system configurations. Simulation demonstrates the feasibility and accuracy of the RRAM-based circuit and our theoretical analysis. Our work proves that RRAM-based IMC holds significant potential for high-complexity nonlinear precoding, addressing the escalating computational demands for future communications.

Keywords:

RRAM

memristor

massive MIMO

THP

LQ decomposition

in-memory computing

bit precision

RRAM Circuit-Enabled Nonlinear Precoding and Bit Precision Analysis

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