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SARO: Scalable Attack-Resistant Logic Locking
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DOI：10.1109/TIFS.2021.3092135.png)
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Abstract
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Intellectual property (IP) protection against piracy and reverse engineering (RE) has emerged as a critical area of research in the field of hardware security. Logic locking has been studied as a promising technique to provide robust protection against these attacks. However, a vast body of recent works has presented successful attacks to break existing locking methods in terms of retrieving the secret key and restoring the original functionality. In this paper, we propose SARO, a scalable attack-resistant logic locking that provides a robust functional and structural design transformation process. SARO treats the target circuit as a hypergraph (G), and performs partitioning of G to produce a set of sub-graphs, then applies an efficient Truth Table Transformation (T3) process to each partition. Further, to mitigate specific attacks (such as SAT-based analysis), SARO implements distributed attack resistance, which integrates random SAT-hard functions (obtained from an automatic function generator, RanSAT) into select partitions. RanSAT produces non-biased and non-deterministic design transformations, where added locking mechanisms are not distinguishable from the original circuit. Finally, it implements a concept of a derived key generation that simultaneously helps to minimize the required key size through judicious reuse of key bits, as well as enhancing the structural alterations. Unlike state-of-the-art logic locking solutions, which focus on primarily enhancing robustness against functional query-based attacks, the proposed transformation steps provide the following unique benefits: (1) high scalability to large designs obtained through partitioning; (2) high structural obfuscation leading to resistance to structural attacks; and (3) low key size, while maintaining strong resistance against functional attacks. To quantitatively represent the level of structural and functional transformation, we also propose the T3(metric). We evaluate SARO on ISCAS85 and EPFL benchmarks, and provide comprehensive security and performance analysis of our proposed framework.
Keywords:
Logic gates
Measurement
Hardware
Security
Resistance
Tools
Switching circuits
Hardware obfuscation
logic locking (LL)
SARO
scalable
RanSAT
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