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Scalable Wavefront Parallel Streaming Deblocking Filter Hardware for HEVC Decoder
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DOI：10.1109/TCE.2019.2960565.png)
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Abstract
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The proposed work aims to design a Wavefront Parallel Processing (WPP) based streaming Deblocking Filter (DBF) architecture for High-Efficiency Video Coding (HEVC). This architecture supports scalable pipeline stages such as 1, 2, 4 and 8 with Coding Unit (CU) sizes, i.e., 8 x 8, 16 x 16, 32 x 32 and 64 x 64 Largest Coding Unit (LCU) processing respectively. Based on the requirements of speed and area of a consumer electronic application, one of the aforementioned sizes of CU or LCU is selected. The hardware uses an intelligent Memory Organization (MO) based on WPP technique with restructured CUs/LCU size without having any neighboring block dependencies. The proposed designs are implemented on an Application-Specific Integrated Circuit (ASIC) using 180-nm technology and Field Programmable Gate Array (FPGA). Experimental results show that the 32 x 32 and 64 x 64 block processing hardware decreases the processing cycles (128, 96) with the gate count of 286.47K and 744.13K respectively. Similarly, CUs 8 x 8, 16 x 16 consume 512 and 176 processing clock cycles with an equivalent gate count of 90.72K and 194.97K respectively. The performance of proposed hardware compared with the previous works in terms of area and speed. The results show that the proposed hardware can process 4K Ultra High Definition (UHD) video frames at the rate of 50 fps at 300 MHz.
Keywords:
High efficiency video coding (HEVC)
deblocking filter (DBF)
wavefront parallel processing (WPP)
field programmable gate array (FPGA)
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