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Segmented Pre-Computation-Based CAM for Power-Efficient High-Speed Applications
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DOI：10.1109/tcsi.2026.3682601.png)
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Abstract
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This high-speed and power-efficient content addressable memory employs parallel lookups to expedite matching without compromising power consumption. It introduces three significant innovations: i. pre-computation based operation, which enhances search speed by eliminating mismatch conditions only in 4-bit comparisons; ii. a hybrid match line structure that strategically balances power and delay, amalgamating the high-speed attributes of NOR with the low-power characteristics of NAND; and iii. a control technique that processes segments to the final match line. Performance metrics exhibit significant enhancements when these methodologies are seamlessly integrated. Employing 45 nm CMOS technology, the design accommodates diverse process voltages, temperatures, and frequencies for a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$64\times 32$ </tex-math></inline-formula> memory array. Monte Carlo simulations validate design stability. The proposed architecture surpasses the leading benchmark in speed and power-delay-product by 62.85% and 99.78%, respectively. The proposed architecture supports repeated data searches at frequencies up to 2 GHz, which has the potential to revolutionize search in high-performance computing, mobile devices, and IoT applications.
Keywords:
Content addressable memory
high-speed search
hybrid match lines
pre-computing
pre-charge free CAM
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