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SIGNED MULTIPLICATION ARCHITECTURE USING VEDIC URDHVA TIRYAGBHYAM ALGORITHM
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AI
DOI：10.2298/FUEE2601137K.png)
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Abstract
En 中文
This paper introduces a novel architecture for signed multiplication, representing a significant advancement in VLSI design for high-end computation. We have implemented signed number multiplier numbers using the Urdhva Tiryagbhyam (UT) algorithm. The purpose of the proposed architecture is to overcome the limitations of previous approaches, through the integration of Virtex-7 and Spartan-7 hardware, in addition to improving power and delay performance. As a result of using vertical and crosswise techniques, the proposed parallel multiplication scheme for signed numbers is implemented in this paper. We have synthesized and simulated this structure using Vivado 2020.1 software and Virtex-7 and Spartan-7 FPGA devices for low-power VLSI computational applications, such as checking the speed and delay of the design post-layout. A comparison is made between the proposed design and existing architectures in terms of area, delay, and power consumption. According to the results, the proposed architecture improves speed by 40% over prior architectures. For faster computing applications, a high-speed proposed multiplier will be useful for complex design architecture. The work contributes significantly to the improvement of high-performance computing and digital signal processing.
Keywords:
Computational
Vedic multiplier
High performance computing
FPGA
System design
urdhva tiryagbhyam
Journal
F
IF:
0.7
Papers:
34
Citations:
211